Article
Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology
Authors
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Abstract
The aspire of the manuscript is to apply a 14T Full adder unit, so as to make use of low power by means of XOR and XNOR gate. The 4-bit binary adder is constructed in ripple carry adder arrangement. It has been designed for low power utilization in reducing the number of transistors. The power utilization can be reduced by 49% with proposed FA compared to regular FA. All simulation results have been carried out with 32 nm CMOS technology. The simulation outcome of 1-bit adder proposed FA shows that the proposed FA has low power utilization. The hardware implementation of 14T FA is done with Deep Submicron Technology.
Keywords
FA, XOR, XNOR, FPGA
Citation
Nayani, A. K., Fairooz, S., Subbaiah, G. V., Rajeshwari, B., & Lakshmaiah, D. (2021). Low-power CMOS 1-Bit full adder using FPGA KIT & DSM technology. Turkish Journal of Computer and Mathematics Education, 12(3), 5720–5725.
A. K. Nayani, S. Fairooz, G. V. Subbaiah, B. Rajeshwari and D. Lakshmaiah, “Low-power CMOS 1-Bit full adder using FPGA KIT & DSM technology,” Turkish Journal of Computer and Mathematics Education, vol. 12, no. 3, pp. 5720–5725, 2021.
Nayani AK, Fairooz S, Subbaiah GV, Rajeshwari B, Lakshmaiah D. Low-power CMOS 1-Bit full adder using FPGA KIT & DSM technology. Turkish Journal of Computer and Mathematics Education. 2021;12(3):5720–5725.
Nayani, A. K., Fairooz, S., Subbaiah, G. V., Rajeshwari, B. and Lakshmaiah, D. (2021), ‘Low-power CMOS 1-Bit full adder using FPGA KIT & DSM technology’, Turkish Journal of Computer and Mathematics Education, 12(3), pp. 5720–5725.
Nayani, A.s Keerthi, et al. “Low-power CMOS 1-Bit Full Adder Using FPGA KIT & DSM Technology.” Turkish Journal of Computer and Mathematics Education, vol. 12, no. 3, 2021, pp. 5720–5725.
Nayani, A.s Keerthi, Shaik Fairooz, Gandham Venkata Subbaiah, B. Rajeshwari, and Dayadi Lakshmaiah. “Low-power CMOS 1-Bit Full Adder Using FPGA KIT & DSM Technology.” Turkish Journal of Computer and Mathematics Education 12, no. 3 (2021): 5720–5725.
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Published by: Engineering Journals
