Article
ECC Processor for Design and Implementation of High-Speed RSD
Authors
, and
Abstract
In this paper, an exportable application-particular guideline set elliptic curve cryptography (ECC) processor in view of excess marked digit portrayal is proposed. The processor utilizes broad pipelining methods for Karatsuba–Ofman strategy to accomplish high throughput duplication. Besides, an effective measured snake without correlation and a high throughput secluded divider, which brings about a short data path for expanded recurrence, are executed. The processor bolsters the suggested NIST curve P256 and depends on an expanded NIST decrease plot. The proposed processor performs single point augmentation utilizing focuses in relative directionsin less time.
Keywords
Elliptic curve cryptography, FPGA, Redundant signed digits, Arithmetic unit
Citation
Bochu, D., Prakash, I., & Jeevana, K. J. (2019). ECC processor for design and implementation of high-speed RSD. Turkish Journal of Computer and Mathematics Education, 10(3), 787–795.
D. Bochu, I. Prakash and K. J. Jeevana, “ECC processor for design and implementation of high-speed RSD,” Turkish Journal of Computer and Mathematics Education, vol. 10, no. 3, pp. 787–795, 2019.
Bochu D, Prakash I, Jeevana KJ. ECC processor for design and implementation of high-speed RSD. Turkish Journal of Computer and Mathematics Education. 2019;10(3):787–795.
Bochu, D., Prakash, I. and Jeevana, K. J. (2019), ‘ECC processor for design and implementation of high-speed RSD’, Turkish Journal of Computer and Mathematics Education, 10(3), pp. 787–795.
Bochu, Dharmendar, et al. “ECC Processor for Design and Implementation of High-speed RSD.” Turkish Journal of Computer and Mathematics Education, vol. 10, no. 3, 2019, pp. 787–795.
Bochu, Dharmendar, Immadisettyvenkata Prakash, and Kale Jyothi Jeevana. “ECC Processor for Design and Implementation of High-speed RSD.” Turkish Journal of Computer and Mathematics Education 10, no. 3 (2019): 787–795.
Export citation
Published by: Engineering Journals


