Turkish Journal of Computer and Mathematics Education
Journal license

Journal

Turkish Journal of Computer and Mathematics Education


Volume
& Issue

Volume 10, Issue 3


Published
on


Pages

787-795


DOI

Article

ECC Processor for Design and Implementation of High-Speed RSD


Authors

Dharmendar Bochu Affiliation:
Associate Professor, Department of ECE, Siddhartha Institute of Technology and Sciences, Hyderabad, Telangana, India
, Immadisettyvenkata Prakash Affiliation:
Associate Professor, Department of ECE, Siddhartha Institute of Technology and Sciences, Hyderabad, Telangana, India
and Kale Jyothi Jeevana Affiliation:
Assistant Professor, Department of ECE, Siddhartha Institute of Technology and Sciences, Hyderabad, Telangana, India


Abstract

In this paper, an exportable application-particular guideline set elliptic curve cryptography (ECC) processor in view of excess marked digit portrayal is proposed. The processor utilizes broad pipelining methods for Karatsuba–Ofman strategy to accomplish high throughput duplication. Besides, an effective measured snake without correlation and a high throughput secluded divider, which brings about a short data path for expanded recurrence, are executed. The processor bolsters the suggested NIST curve P256 and depends on an expanded NIST decrease plot. The proposed processor performs single point augmentation utilizing focuses in relative directionsin less time.


Keywords

Elliptic curve cryptography, FPGA, Redundant signed digits, Arithmetic unit


Citation

Bochu, D., Prakash, I., & Jeevana, K. J. (2019). ECC processor for design and implementation of high-speed RSD. Turkish Journal of Computer and Mathematics Education, 10(3), 787–795.

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