Adders are a crucial component of microprocessors' data channel logic; therefore, their design has been at the forefront of VLSI research for quite some time. While EDA flow helps designers get closer to an optimal adder architecture, it isn't always enough. The design space is huge, which is why this is the case. A machine learning-based strategy was offered in earlier studies as a means to investigate the design space. Weak feature representations and an inefficient two-stage learning loop cause prefix adder structures to underperform. A multi-branch framework that combines a variational graph autoencoder and a neural process (NP) is first demonstrated; this is the graph neural process.