In BIST design the ATPG is the one of critical thought. The execution likewise the relies on upon the suitable ATPG era . In our paper we propose the novel technique for multiple single input change (MSIC) test designs that are planned for the sweep chain. So as to build up any technique, we have to consider the region and power angles for the progressed VLSI plans, and furthermore ready to play out the test proficiently utilizing test -per-clock and the test-per-check procedures. The correct investigation for the plan of MSIC additionally gave. The execution assessment is finished by planning in VERILOG and utilizing reenactment and union instruments like Model-sim 6.6 and Xilinx14.3 the yield exhibit and check ISCAS benchmarks can be utilized. The proposed technique gives proficient blame scope without increment of BIST design and test time.