One of the most indispensible parts of many modern VLSI (Very Large Scale Integration) designs is Static Random Access Memory (SRAM), due to its low consumption of power, higher speed and it dominates the silicon area in various applications. Normally the ICs (Integrated Chips) are most complicated for increasing the chip density and decreasing chip size. Hence for overcoming these issues the SRAM will be implemented. In this paper the efficient back gate biasing based SRAM Array with row and column selection is presented. Address decoder is used to generate the row address and column address. The novel low power 6T SRAM cell will be utilized for designing the SRAM array for improving the read stability. The energy efficiencies of SRAM will be attained with the wider structure of SRAM array with less number of rows compared to columns especially at less supply voltage. In 6T SRAM cell, the write operation is performed while charging and discharging the single BL (Bit Line), that will reduce the consumption of dynamic power. The simulation results will show that a better efficiency will be achieved for same bit density of SRAM as well as same supply voltage. SRAM array also reduces the area by minimizing the number of transistors used to implement SRAM array design.