Traffic patterns significantly effects the performance of networks -on-chip (NoC ) architectures. The rapid increase and unpredictable behaviour of traffic may cause delay in high -speed packet transmission that ultimately increase the cost of the system. Choice of topology is also a measure concern to cope up the uneven traffic patterns. In this paper, an analytical and experimental evaluation of various NoC architecture is carried out in terms of their performance capabilities. To evaluate the performance of the considered architectures, a number of architectural characteristics such a s network diameter, degree and cost are evaluated and simulation results are obtained under different traffic patterns. An organizational model is proposed while considering the problem of delay in traffic engineering using different NoC architectures. The BookSim simulator is chosen for evaluating parameters like network latency, throughput and execution time. This is carried out by implementing different interconnection networks under five routing evaluation traffic models with appropriate selection of NoC architectures. Effect of virtual channels (VC) is also assessed under same traffic pattern. Four regular topologies are used to carryout comparative studies namely standard 4 x 4 Mesh, Folded Torus, DIMB network and recently introduced Linearly Extensib le Triangle Network (LECΔ) . Based on the study carried out a high - level modeling of NoCs with appropriate topology is evaluated under certain network parameters used to evaluate the performance of NoC architectures. Research in this direction shows that the number of cores in NoC architectures with appropriate routing techniques effectively reduce the cost and complexity of the system without losing the performance of architecture.