Design of high speed and low cost Novel Hybrid Adder for VLSI applications is implemented in this paper. In VLSI chips adder is used as critical element for implementation. Adder's plays major role in circuits of ALUs, Floating point arithmetic units, memory addressing and program countin g. Trade off occurred between the circuits is reduced because of Novel adders. Size of the parallel circuit is determined based on the nodes . VLSI synthesis tool is utilized to simulate Novel adder. E ffective results are obtained compared with RCA.