Article
Scale Factor and Latency Analysis in CORDIC Processing Unit
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Abstract
Virtual laptop, cordic or synchronized, is a fast, quick, environmentally friendly algorithm for many applications used for the processing of digital signs. It typically uses an exquisite computing technique for the fixation of the trigonometrically relationships worried about rotation around plane coordinates and rectangular to polar shape conversion, developed for actual airborne calculations. It contains a one-of-a-kind serial mathematics unit having 3 shift registers, 3 adders/sub tractors, appearance-up table and remarkable interconnections.
Keywords
CORDIC, HDL FPGA, DCT, Latency
Citation
Sharma, N. K., Rathore, S., & Jain, J. (2021). Scale factor and latency analysis in CORDIC processing unit. Turkish Journal of Computer and Mathematics Education, 12(2), 3155–3160.
N. K. Sharma, S. Rathore and J. Jain, “Scale factor and latency analysis in CORDIC processing unit,” Turkish Journal of Computer and Mathematics Education, vol. 12, no. 2, pp. 3155–3160, 2021.
Sharma NK, Rathore S, Jain J. Scale factor and latency analysis in CORDIC processing unit. Turkish Journal of Computer and Mathematics Education. 2021;12(2):3155–3160.
Sharma, N. K., Rathore, S. and Jain, J. (2021), ‘Scale factor and latency analysis in CORDIC processing unit’, Turkish Journal of Computer and Mathematics Education, 12(2), pp. 3155–3160.
Sharma, Nitesh Kumar, et al. “Scale Factor and Latency Analysis in CORDIC Processing Unit.” Turkish Journal of Computer and Mathematics Education, vol. 12, no. 2, 2021, pp. 3155–3160.
Sharma, Nitesh Kumar, Shanti Rathore, and Jainendra Jain. “Scale Factor and Latency Analysis in CORDIC Processing Unit.” Turkish Journal of Computer and Mathematics Education 12, no. 2 (2021): 3155–3160.
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Published by: Engineering Journals


