The paper outlines the utmost importance of energy-efficient devices for IoT applications and recommends a dual edge-triggered TSPC flip-flop in fully-static mode at 45nm technology with low supply rail carried out in CMOS using MENTOR GRAPHICS tool. The proposed flip-flop proved to be energy efficient compared to traditional double and single edge-triggered flip-flops in terms of latency, power, the figure of merit and area for IoT applications. A comparison of two types of dual-edge triggered flip-flops are analyzed concerning the mentioned performance metrics and deduces the best flip-flop for IoT applications. Clock overlap issues are turning down in dual edge-triggered TSPC flip-flop compared with a conventional dual edge-triggered flip-flop in full static mode and allow stringent operation at 1V supply rail that delivers 1.14uW power, 0.60fJ figure of merit and 531.99ps latency at 45nm CMOS.