This research presents the design of a 2 -bit binary Magnitude Comparator (MC) using Conventional CMOS (CCMOS) logic and Pass Transistor Logic (PTL). The proposed MC design is subjected to simulation and c ompared with five other existing MC designs to assess its performance. The results indicate that the proposed 2 -bit MC design exhibits significant improvements in terms of speed and power efficiency. This enhancement results in a notable improvement in the Power Delay Product (PDP). As a result, the proposed MC design stands as a highly effective alternative to existing designs. The rapid evolution of circuit design has introduced various methodologies for VLSI circuit implementation, including CCMOS, PTL, and Transmission Gate Logic (TGL). Consequently, various MC designs have been developed to meet diverse requirements. The PTL -based 2 -bit MC design utilizes 40 transistors; however, it suffers from voltage degradation, especially in lower CMOS technology n odes, leading to reduced drive power. To address these issues, new designs have emerged.