The Modified Vedic Multiplier is a multiplication algorithm based on ancient Vedic Mathematics principles. The algorithm uses a series of vertical and crosswise calculations to perform multiplication. The Modified HSCG -SCG Adder is an improved version of a conventional binary adder, which uses a decoder to generate partial products and a carry tree to produce the final result. The Modified Vedic Multiplier using Modified HSCG -SCG Adder has advantages over traditional multipliers, such as reduced latency, reduced power consumption, and higher speed. It is suitable for use in applications that require high -speed multiplication, such as digital signal processing, image processing, and cryptography. The implementation of this algorithm can be done using Verilog HDL, a hardware description language. The design can be simulated and tested using a hardware simulator such as Vivado.